The invention relates to an arrangement for generating an analog angle-modulated carrier signal having a substantially constant amplitude in response to data signals of a given symbol frequency 1/T. The arrangement comprises a clock circuit synchronized with the symbol frequency 1/T for producing a first clock signal having a frequency q/T, where q is an integer greater than 1; a first read-only memory for storing in addressable locations digital numerical values representing modulation parameters of the angle-modulated carrier signal; an addressing circuit controlled by the first clock signal and responsive to a predetermined number of consecutive data symbols for producing addresses with a rate q/T for reading the stored values from the locations of the first read-only memory; and a signal processor connected to the first read-only memory processing the read values to form the analog angle-modulated carrier signal.
Such an arrangement is known from the article by De Jager and Dekker on TFM (Tamed Frequency Modulation) in IEEE Transactions on Communications, Vol. COM-26, No. 5, May 1978, pages 534-542 (see FIG. 15) and U.S. Pat. No. 4,229,821 (see FIG. 18). In these known arrangements, the values stored in the first read-only memory represent two modulation parameters cos [.phi.(t)] and sin [.phi.(t)], where .phi.(t) is the phase of the angle-modulated carrier signal which is determined by a filtered version of a predetermined number of consecutive data symbols. In the signal processor following this read-only memory, the analog signals corresponding with these two modulation parameters are obtained with the aid of the DAC-circuits (Digital-to-Analog Conversion circuits). The two analog signals are applied via two low-pass filters for suppressing unwanted signal components at the frequency q/T and multiples thereof to an analog quadrature modulation circuit, where they are multiplied by two carriers in phase quadrature by means of two product modulators and the angle-modulated carrier signal is obtained by means of an adder connected to the product modulators.
As the interface between the digital and analog signal processing sections are located immediately after the first read-only memory, this known arrangement has a pronounced hybrid structure and particularly high requirements are imposed on the circuit implementation of the analog section, both as regards the equality of the amplitude and the phase characteristics of the two signal paths and the unavoidable d.c. voltage off-sets occurring therein, and as regards the accuracy of the phase quadrature of the two carriers to prevent undesired amplitude and phase variations, undesired sidebands and insufficient carrier suppression from occurring in the angle-modulated carrier signal at the output of this arrangement.
A possible solution to the above-mentioned disadvantage is to replace the constituent parts of the analog quadrature modulation circuit (product modulators, carrier oscillator and adder) by their digital equivalents which are known per se, to arrange these equivalents for processing signal samples at the rate q/T of the first clock signal and to connect directly the digital quadrature modulation circuit thus obtained to the first read-only memory. The interface between the digital and analog sections is then shifted to the output of the quadrature modulation circuit and consequently only one DAC circuit is required for obtaining the analog angle-modulated carrier signal.
Although an arrangement is obtained which has a predominantly digital structure and which consequently is attractive for monolithic integration, it appears in practice that the requirement of a DAC-circuit as the interface between digital and analog sections generally limits the maximum data symbol rate 1/T allowable for the digital section. In addition, a high-speed DAC-circuit is not very suitable for monolithic integration and as a module it is proportionally more expensive than the digital integrated circuits for common logic functions.